View CY28339ZXC_2394388.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

intel ck408 mobile clock synthesize r cy28339 rev 1.0, november 25, 2006 page 1 of 17 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax:(408) 855-0550 www.spectralinear.com features ? compliant with intel ? ck 408 rev 1.1 mobile clock synthesizer specifications 3.3v power supply two differential cpu clocks nine copies of pci clocks three copies configurab le pci free-running clocks two 48 mhz clocks (usb, dot) five/six copies of 3v66 clocks one vch clock one reference clock at 14.318 mhz smbus support with read-back capabilities ideal lexmark profile spread spectrum electromag- netic interference (emi) reduction dial-a-frequency? features dial-a-db? features 48-pin tssop package note: 1. tclk is a test clock driven on the xtal_in input during test mode. m = driven to a level between 1.0v and 1.8v. if the s2 pin is at a m level during power-up, a 0 state will be latched into the device?s internal state register. table 1. frequency table [1] s2 s1 cpu (1:2) 3v66 66buff(0:2)/ 3v66(0:4) 66in/3v66?5 pcif, pci ref usb/ dot 1 0 100m 66m 66in 66-mhz clock input 66in/2 14.318m 48m 1 1 133m 66m 66in 66-mhz clock input 66in/2 14.318m 48m 0 0 100m 66m 66m 66m 33 m 14.318m 48m 0 1 133m 66m 66m 66m 33 m 14.318m 48m m 0 tclk/2 tclk/4 tclk/4 tclk/4 tclk/8 tclk tclk/2 pin configuration block diagram vdd_ref cput1:2 cpuc1:2 pcif xtal pll ref freq x2 x1 ref vdd_pci usb (48mhz) vch_clk/ 3v66_1 osc vdd_cpu cpu_stop# sclk pci0:2 pci_stop# stop clock control stop clock control pll 1 smbus logic dot (48mhz) pd# s1:2 vdd_48mhz sdata vdd_3v66 3v66_0:1 3v66_2:4/ divider network 3v66_5/ 66in pwr pwr pwr pwr pwr pll 2 pwr 66buff0:2 gate vtt_pwrgd## /2 top view 1 2 3 4 5 6 7 8 9 10 11 12 25 28 27 xin 26 13 14 15 16 17 18 19 20 21 22 23 24 37 36 35 34 33 29 30 31 32 40 39 38 xout gnd_ref pci7 41 44 43 42 45 48 47 46 pci2 66buff0/3v66_2 gnd_core sclk gnd_48 mhz cput2 cpu_stop# gnd_pci vdd_3v66 66in/3v66_5 3v66_0 usb_48mhz cpuc1 vdd_ref pci8 pcif pci0 pci1 vdd_pci pci4 pci5 pci6 gnd_3v66 66buff1/3v66_3 66buff2/3v66_4 pd# vdd_core vtt_pwrgd# sdata gnd_3v66 vdd_3v66 pci_stop# 3v66_1/vch vdd_48 mhz dot_48mhz s2 iref cpuc2 vdd_cpu gnd_cpu cput1 vdd_cpu s1 ref cy28339 pci4:8
cy28339 rev 1.0, november 25, 2006 page 2 of 17 pin definitions pin number name i/o description 47 ref0 3.3v 14.318 mhz clock output . 1xin 14.318 mhz crystal input . 2xout 14.318 mhz crystal input . 43, 42, 39, 38 cput1,cpuc1 cput2, cpuc2 differential cpu clock outputs . 29 3v66_0 3.3v 66 mhz clock output . 31 3v66_1/vch 3.3v selectable through smbus to be 66 mhz or 48 mhz . 20 66in/3v66_5 66 mhz input to buffered 66buff and pci or 66 mhz clock from internal vco . 17, 18, 19 66buff [2:0] /3v66 [4:2] 66 mhz buffered outputs from 66input or 66 mhz clocks from internal vco . 6pcif 33 mhz clocks divided down from 66input or divided down from 3v66 ; pcif default is free-running. 8, 9, 10, 12, 13, 14, 4, 5 pci [0:2] pci [4:6] pci [7:8] pci clock outputs divided down from 66input or divided down from 3v66 ; pci [7:8] are configurable as free-running pci through smbus. [2] 35 usb_48m fixed 48 mhz clock output . 34 dot_48m fixed 48 mhz clock output . 36 s2 special 3.3v three-level input for mode selection . 46 s1 3.3v lvttl inputs for cpu frequency selection . 37 iref a precision resistor is attached to this pin which is connected to the internal current reference . 21 pd# 3.3v lvttl input for power_down# (active low) . 30 pci_stop# 3.3v lvttl input for pci_stop# (active low) . 45 cpu_stop# 3.3v lvttl input for cpu_stop# (active low) . 24 vtt_pwrgd# 3.3v lvttl input is a level-sensitive st robe used to determine when s[2:1] inputs are valid and ok to be sampled (active low) . once vtt_pwrgd# is sampled low, the status of this input will be ignored. 25 sdata smbus-compatible sdata . 26 sclk smbus-compatible sclk . 11, 15, 28, 40, 44, 48 vdd_pci, vdd_3v66, vdd_cpu,vdd_ref 3.3v power supply for outputs . 33 vdd_48 mhz 3.3v power supply for 48 mhz . 22 vdd_core 3.3v power supply for phase-locked loop (pll) . 3, 7, 16, 27, 32, 41 gnd_ref, gnd_pci, gnd_3v66, gnd_iref, gnd_cpu ground for outputs . 23 gnd_core ground for pll . note: 2. pci3 is internally disabled and is not accessible.
cy28339 rev 1.0, november 25, 2006 page 3 of 17 two-wire smbus control interface the two-wire control interface implements a read/write slave only interface according to smbus specification. the device will accept data written to the d2 address and data may read back from address d3. it will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device. serial control registers following the acknowledge of the address byte, two additional bytes must be sent: 1. ?command code? byte 2. ?byte count? byte. although the data (bits) in the command is considered ?don?t care,? it must be sent and will be acknowledged. after the command code and the byte count have been acknowl- edged, the sequence (byte 0, byte 1, and byte 2) described below will be valid and acknowledged. byte 0: cpu clock register [3,4] bit @pup name description 7 0 spread spectrum enable. 0 = spread off, 1 = spread on. this is a read and write control bit. 6 0 cpu clock power-down mode select. 0 = drive cput to 2x iref and drive cpuc low 1 = tri-state all cpu outputs. this is only applicable when pd# is low. it is not applicable to cpu_stop#. 5 0 3v66_1/vch 3v66_1/vch frequency select 0 = 66m selected, 1 = 48m selected. this is a read and write control bit. 4 reserved 3 hw pci_stop# reflects the current value of the internal pci_stop# function when read. internally pci_stop# is a logical and function of the internal smbus register bit and the external pci_stop# pin. 2 hw s2 frequency select bit 2. reflects the value of s2. this bit is read-only. 1 hw s1 frequency select bit 1. reflects the value of s1. this bit is read-only. 01 reserved byte 1: cpu clock register bit @pup name description 71 reserved 6 0 cput1, cpuc1 cput2, cpuc2 cput/c output functionality c ontrol when cpu_stop# is asserted. 0 = drive cput to 6x iref and drive cpuc low 1 = three-state all cpu outputs. this bit will override byte0,bit6 such that even if it is 0, when pd# goes low the cpu outputs will be three-stated. 5 0 cput2, cpuc2 cput/c2 functionality control when cpu_stop# is asserted. 0 = stopped low,1 = free running. this is a read and write control bit. 4 0 cput1, cpuc1 cput/c1 functionality control when cpu_stop# is asserted. 0 = stopped low, 1 = free running. this is a read and write control bit. 30 reserved 2 1 cput2, cpuc2 cput/c2 output control. 0 = disable, 1 = enabled. this is a read and write control bit. 1 1 cput1, cpuc1 cput/c1 output control. 0 = disable, 1 = enabled. this is a read and write control bit. 01 reserved notes: 3. pu = internal pull-up. pd = internal pull-down. t = tri-level logic input with valid logic voltages of low = < 0.8v, t = 1.0 ? 1.8v and high = > 2.0v. 4. the ?pin#? column lists the relevant pin number where applicable. the ?@pup? column gives the default state at power-up.
cy28339 rev 1.0, november 25, 2006 page 4 of 17 byte 2:pci clock control register (all bits are read and write functional) bit @pup name description 7 0 ref ref output control. 0 = high strength, 1 = low strength. 6 1 pci6 pci6 output control. 0 = forced low, 1 = enabled 5 1 pci5 pci5 output control. 0 = forced low, 1 = enabled 4 1 pci4 pci4 output control. 0 = forced low, 1 = enabled 31 reserved 2 1 pci2 pci2 output control. 0 = forced low, 1 = enabled 1 1 pci1 pci1 output control. 0 = forced low, 1 = enabled 0 1 pci0 pci0 output control. 0 = forced low, 1 = enabled byte 3: pcif clock and 48m control register (all bits are read and write functional) bit @pup name description 7 1 dot_48m dot_48m output control. 0 = forced low, 1 = enabled 6 1 usb_48m usb_48m output control. 0 = forced low,1 = enabled 5 0 pcif pci_stop# control of pcif. 0 = free running, 1 = stopped when pci_stop# is asserted. 4 1 pci8 pci_stop# control of pci8. 0 = free running, 1 = stopped when pci_stop# is asserted. 3 1 pci7 pci_stop# control of pci7. 0 = free running, 1 = stopped when pci_stop# is asserted. 2 1 pcif pcif output control. 0 = forced low, 1 = running 1 1 pci_8 pci_8 output control. 0 = forced low, 1 = running 0 1 pci_7 pci_7 output control. 0 = forced low, 1 = running byte 4: control register (all bits are read and write functional) bit @pup name description 7 0 ss2 spread spectrum control bit. 0 = down spread, 1 = center spread). 60 reserved. set = 0. 5 1 3v66_0 3v66_0 output enable. 0 = disable, 1 = enabled 4 1 3v66_1/vch 3v66_1/vch output enable. 0 = disable, 1 = enabled 3 1 3v66_5 3v66_5 output enable. 0 = disable, 1 = enabled 2 1 19 66buff2/3v66_4 output enable. 0 = disable, 1 = enabled 1 1 18 66buff1/3v66_3 output enable. 0 = disable, 1 = enabled 0 1 66buff0/3v66_2 66buff0/3v66_2 output enable. 0 = disable, 1 = enabled byte 5:clock control register (all bits are read and write functional) bit @pup name description 7 0 ss1 spread spectrum control bit. 6 1 ss0 spread spectrum control bit. 5 0 66in to 66m delay control msb. 4 0 66in to 66m delay control lsb. 30 reserved. set = 0. 2 0 dot_48m dot_48m edge rate control. when set to 1, the edge is slowed by 15%. 10 reserved. set = 0. 0 0 usb_48m usb_48m edge rate control. when set to 1, the edge is slowed by 15%. byte 6: silicon signature register [5] (all bits are read-only) bit @pup name description
cy28339 rev 1.0, november 25, 2006 page 5 of 17 7 0 revision = 0001 60 50 41 3 0 vendor code = 0011 20 11 01 byte 7: reserved register bit @pup name description 7 0 reserved. set = 0. 6 0 reserved. set = 0. 5 0 reserved. set = 0. 4 0 reserved. set = 0. 3 0 reserved. set = 0. 2 0 reserved. set = 0. 1 0 reserved. set = 0. 0 0 reserved. set = 0. byte 8: dial-a-frequency control register n bit @pup name description 70 reserved. set = 0. 6 0 n6, msb these bits are for programming the pll?s internal n register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clo cks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50n5 40n4 30n3 20n2 10n3 00n0, lsb byte 9: dial-a-frequency control register r bit @pup name description 70 reserved. set = 0. 6 0 r5, msb these bits are for programming the pll?s internal r register. this access allows the user to modify the cpu frequency at very high resolution (accuracy). all other synchronous clocks (clo cks that are generated from the same pll, such as pci) remain at their existing ratios relative to the cpu clock. 50r4 40r3 30r2 20r1 10r0 00 daf_enb r and n register mux selection. 0 = r and n values come from the rom. 1 = data is loaded from daf (smbus) registers. note: 5. when writing to this register, the device will acknowledge the write operation, but the data itself will be ignored. byte 6: silicon signature register [5] (all bits are read-only)
cy28339 rev 1.0, november 25, 2006 page 6 of 17 dial-a-frequency features smbus dial-a-frequency feature is available in this device via byte8 and byte9. p is a large-value pll constant that depends on the frequency selection achieved through the hardware selectors (s1, s0). p value may be determined from table 2 . dial-a-db features smbus dial-a-db feature is available in this device via byte8 and byte9. spread spectrum clock generation (sscg) spread spectrum is a modulation technique used to minimizing emi radiation generated by repetitive digital signals. a clock presents the greatest emi energy at the center frequency it is generating. spread spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. this technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of emi reduction). in this device, spread spectrum is enabled by setting specific register bits in the smbus control bytes. ta ble 3 is a listing of the modes and percentages of spread spectrum modulation that this device incorporates. special functions pcif and ioapic clock outputs the pcif clock outputs are intended to be used, if required, for systems ioapic clock functionality. any two of the pcif clock outputs can be used as ioapic 33-mhz clock outputs. they are 3.3v outputs will be divided down via a simple resistive voltage divider to meet specific system ioapic clock voltage requirements. in the event that these clocks are not required, they can be used as general pci clocks or disabled via the assertion of the pci_stop# pin. 3v66_1/vch clock output the 3v66_1/vch pin has a dual functionality that is selectable via smbus. configured as drcg (66m), smbus byte0, bit 5 = ?0? the default condition for this pin is to power-up in a 66m operation. in 66m operation this output is sscg-capable and when spreading is turned on, this clock will be modulated. configured as vch (48m), smbus byte0, bit 5 = ?1? in this mode, output is configured as a 48-mhz non-spread spectrum output that is phase-aligned with other 48m outputs (usb and dot) to within 1-ns pin-to-pin skew. the switching of 3v66_1/vch into vch mode occurs at system power-on. when the smbus bit 5 of byte 0 is programmed from a ?0? to a ?1,? the 3v66_1/vch output may glitch while transitioning to 48m output mode. pd# (power-down) clarification the pd# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. pd# is an asynchronous active low input. this signal is synchronized internally to the device powering down the clock synthesizer. pd# is an asynchronous function for powering up the system. when pd# is low, all clocks are driven to a low value and held there and the vco and plls are also powered down. all clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ?stopped? state. pd# assertion when pd# is sampled low by two consecutive rising edges of the cpuc clock, then on the next high-to-low transition of pcif, the pcif clock is stopped low. on the next high-to-low transition of 66buff, the 66buff clock is stopped low. from this time, each clock will stop low on its next high-to-low transition, except the cput clock. the cpu clocks are held with the cput clock pin driven high with a value of 2 iref, and cpuc undriven. after the last clock has stopped, the rest of the generator will be shut down. table 2. p value s(1:0) p 0 0 32005333 0 1 48008000 1 0 96016000 1 1 64010667 table 3. spread spectrum ss2 ss1 ss0 spread mode spread% 0 0 0 down +0.00, ?0.25 0 0 1 down +0.00, ?0.50 0 1 0 down +0.00, ?0.75 0 1 1 down +0.00, ?1.00 1 0 0 center +0.13, ?0.13 1 0 1 center +0.25, ?0.25 1 1 0 center +0.37, ?0.37 1 1 1 center +0.50, ?1.50 figure 1. unbuffered mode ? 3v66_0 to pci and pcif phase relationship pci pci_f tpci 3v66-0
cy28339 rev 1.0, november 25, 2006 page 7 of 17 pci 33mhz pwrdwn# cput 133mhz cpuc 133mhz ref 14.318mhz usb 48mhz 3v66 figure 2. power-down assertion timing waveforms ? unbuffered mode 66buff pcif pwrdwn# cpu 133mhz cpu# 133mhz 3v66 66in ref 14.318mhz usb 48mhz figure 3. power-down assertion timing waveforms figure ? buffered mode
cy28339 rev 1.0, november 25, 2006 page 8 of 17 pd# deassertion the power-up latency between pd# rising to a valid logic ?1? level and the starting of all clocks is less than 3.0 ms. cpu_stop# clarification the cpu_stop# signal is an active low input used to synchronously stop and start the cpu output clocks while the rest of the clock generator continues to function. cpu_stop# assertion when cpu_stop# pin is asserted, all cput/c outputs that are set with the smbus configuration to be stoppable via assertion of cpu_stop# will be stopped after being sampled by two falling cput/c clock edges. the final state of the stopped cpu signals is cput = high and cpu0c = low. there is no change to the output drive current values during the stopped state. the cput is driven high with a current value equal to (mult 0 ?select?) (iref), and the cpuc signal will not be driven. due to external pull-down circuitry cpuc will be low during this stopped state. cpu 133mhz 3v66 cpu# 133mhz ref 14.318mhz usb 48mhz pcif / apic 33mhz 66in 66buff pwrdwn# 66buff1 / gmch 400us max <1.8ms pci 33mhz 30us min figure 4. power-down deassertion timing waveforms ? buffered mode cpu_stp# cput cpuc cput cpuc figure 5. cpu_stop# assertion waveform
cy28339 rev 1.0, november 25, 2006 page 9 of 17 cpu_stop# deassertion the deassertion of the cpu_stop# signal will cause all cput/c outputs that were stopped to resume normal operation in a synchronous manner (meaning that no short or stretched clock pulses will be produces when the clock resumes). the maximum latency from the deassertion to active outputs is no more than two cpuc clock cycles. three-state control of cpu clocks clarification during cpu_stop# and pd# modes, cpu clock outputs may be set to driven or undriven (tri-state) by setting the corre- sponding smbus entry in bit6 of byte0 and bit6 of byte1. pci_stop# assertion the pci_stop# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator continues to function. the set-up time for capturing pci_stop# going low is 10 ns (t setup ) (see figure 2 .) the pcif clocks will not be affected by this pin if their control bits in the smbus register are set to allow them to be free running. pci_stop# deassertion the deassertion of the pci_stop# signal will cause all pci(0:2, 4:8) and stoppable pcif clocks to resume running in a synchronous manner within two pci clock periods after pci_stop# transitions to a high level. the pci stop function is controlled by two inputs. one is the device pci_stop# pin number 34 and the other is smbus byte 0,bit 3. these two inputs to the function are logically and?ed. if either the external pin or the internal smbus register bit is set low, the stoppable pci clocks will be stopped in a logic low state. reading smbus byte 0,bit 3 will return a 0 value if either of these control bits are set low (which indicates that the devices stoppable pci clocks are not running). cpu_stp# cput cpuc cput cpuc figure 6. cpu_stop# de-assertion waveform pci_stp# pcif 33m pci 33m setup t figure 7. pci_stop# assertion waveform
cy28339 rev 1.0, november 25, 2006 page 10 of 17 iout is selectable depending on implementation. the param- eters above apply to all configurations. vout is the voltage at the pin of the device. the various output current configurations are shown in the host swing select functions table. for all configurations, the deviation from the expected output current is 7% as shown in the current accuracy table. pci_stp# pcif pci setup t figure 8. pci_stop# deassertion waveform figure 9. vtt_pwrgd# timing diagram vid (0:3), sel (0,1) vtt_pwrgd# pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored. vtt_pwrgd# = low delay >0.25ms s1 power off s0 vdda = 2.0v sample inputs straps s2 normal operation wait for <1.8ms enable outputs s3 vtt_pwrgd# = toggle vdd3.3= off figure 10. clock generator power-up/run state program
cy28339 rev 1.0, november 25, 2006 page 11 of 17 charlene: mult0 is fixed at 1. usb_48m and dot_48m phase relationship the usb_48m and dot_48m clocks are in phase. it is under- stood that the difference in edge rate will introduce some inherent offset. when 3v66_1/vch clock is configured for vch (48-mhz) operation it is also in phase with the usb and dot outputs. see figure 11 . 66in to 66buff(0:2) buffered prop delay the 66in to 66buff(0:2) output delay is shown in figure 12 .the tpd is the prop delay from the input pin (66in) to the output pins (66buff[0:2]). the outputs? variation of tpd is described in the ac parameters section of this data sheet. the measurement taken at 1.5v. 66buff(0:2) to pci buffered clock skew figure 13 shows the difference (skew) between the 3v33(0:5) outputs when the 66m clocks are connected to 66in. this offset is described in the group timing relationship and toler- ances section of this data sheet. the measurements were taken at 1.5v. 3v66 to pci un-buffered clock skew figure 1 shows the timing relationship between 3v66_0 and pci(0:2,4:8) and pcif when configured to run in the unbuf- fered mode. table 4. cpu clock current select function board target trace/term z reference r, iref ? vdd (3*rr) output current voh @ z 50 : rr = 330 1%, iref = 3.33ma ioh = 6*iref 1.0v @ 50 50 : rr = 475 1%, iref = 2.32ma ioh = 6*iref 0.7v @ 50 table 5. group timing relationship and tolerances description offset tolerance conditions 3v66 to pci 2.5 ns r 1.0 ns 3v66 leads pci (unbuffered mode) usb_48m to dot_48m skew 0.0 ns r 1.0 ns 0 degrees phase shift 66buff(0:2) to pci offset 2.5 ns r 1.0 ns 66buff leads pci (buffered mode) usb_48m dot_48m figure 11. usb_48m and dot_48m phase relationship 66in 66b tpd figure 12. 66in to 66buff(0:2) output delay figure 66b pci pcif 1.5- 3.5ns figure 13. buffer mode ? 33 v66_0; 66buff(0:2) phase relationship
cy28339 rev 1.0, november 25, 2006 page 12 of 17 buffer characteristics current mode cpu clock buffer characteristics the current mode output buffer detail and current reference circuit details are contained in the previous table of this data sheet. the following parameters are used to specify output buffer characteristics: 1. output impedance of the current mode buffer circuit ? ro (see figure 14 ). 2. minimum and maximum required voltage operation range of the circuit ? vop (see figure 14 ). 3. series resistance in the buffer circuit ? ros (see figure 14 ). 4. current accuracy at given configuration into nominal test load for given configuration. 1.2v 0v iout iout ros ro vdd3 (3.3v +/- 5%) vout = 1.2v max vout slope ~ 1/r 0 figure 14. buffer characteristics table 6. host clock (hcsl) buffer characteristics characteristic min. max. ro 3000 : (recommended) n/a ros vout n/a 1.2v table 7. maximum lumped capacitive output loads clock max load units pci clocks 30 pf 3v66 30 pf 66buff 30 pf usb_48m clock 20 pf dot_48m 10 pf ref clock 50 pf
cy28339 rev 1.0, november 25, 2006 page 13 of 17 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non functional ?65 150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? volts ? jc dissipation, junction to case mil-spec 883e method 1012.1 45 c/w ? ja dissipation, junction to ambient jedec (jesd 51) 15 c/w ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 dc electrical specifications parameter description condition min. max. unit vdd_a , vdd_ref, vdd_pci, vdd_3v66, vdd_48, vdd_cpu 3.3 operating voltage 3.3 5% 3.135 3.465 v i dd3.3v dynamic supply current all frequencies at maximum values ?280ma i pd3.3v power down supply current pd# asserted ? ma c in input pin capacitance ? 5 pf c out output pin capacitance ? 6 pf l in pin inductance ? 7 nh c xtal crystal pin capacitance measured from the xin 30 42 pf ac electrical specifications parameter description condition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ?10.0ns t ccj xin cycle to cycle jitter as an average over 1 p s duration ? 500 ps cpu at 0.7v t dc cput and cpuc duty cycle measured at crossing point v ox 45 55 % t period 66mhz cput and cpuc period measured at crossing point v ox 14.85 15.3 ns t period 100mhz cput and cpuc period measured at crossing point v ox 9.85 10.2 ns t period 133mhz cput and cpuc period measured at crossing point v ox 7.35 7.65 ns t period 200mhz cput and cpuc period measured at crossing point v ox 4.85 5.1 ns t skew any cput/c to cput/c clock skew measured at crossing point v ox ?100ps t ccj cput/c cycle to cycle jitter measured at crossing point v ox ?150ps t r / t f cput and cpuc rise and fall times measured from vol= 0.175 to voh = 0.525v 175 700 ps
cy28339 rev 1.0, november 25, 2006 page 14 of 17 t rfm rise/fall matching determined as a fraction of 2*(t r -t f )/(t r +t f )?20% ' t r rise time variation ? 125 ps ' t f fall time variation ?125ps v ox crossing point voltage at 0.7v swing 280 430 mv cpu at 1.0 volts t dc cput and cpuc duty cycle measured at crossing point v ox 45 55 % t period 66mhz cput and cpuc period measured at crossing point v ox 14.85 15.3 ns t period 100mhz cput and cpuc period measured at crossing point v ox 9.85 10.2 ns t period 133mhz cput and cpuc period measured at crossing point v ox 7.35 7.65 ns t period 200mhz cput and cpuc period measured at crossing point v ox 4.85 5.1 ns t skew any cput/c to cput/c clock skew measured at crossing point v ox ?100ps t ccj cput/c cycle to cycle jitter measured at crossing point v ox ?150ps t r / t f cput and cpuc rise and fall times measured from vol= 0.175 to voh = 0.525v 175 467 ps v ox crossing point voltage at 0.7v swing 510 760 mv se_ ' slew absolute single-ended rise/fall waveform symmetry ?325ps 3v66 t dc 3v66 duty cycle measurement at 1.5v 45 55 % t period 3v66 period measured at crossing point v ox 15.0 15.3 ns t high 3v66 high time measurement at 2.4v 4.95 ? ns t low 3v66 low time measurement at 0.4v 4.55 ? ns t r / t f 3v66 rise and fall times measured between 0.4v and 2.4v 0.5 2.0 ns t skewun- buffered any 3v66 to any 3v66 clock skew measurement at 1.5v ?500ps t skew- buffered any 3v66 to any 3v66 clock skew measurement at 1.5v ?250ps t ccj 3v66 cycle to cycle jitter measurement at 1.5v ? 250 ps 66buff t dc 66buff duty cycle measurement at 1.5v 45 55 % t r / t f 66buff rise and fall times measured between 0.4v and 2.4v 0.5 2.0 ns t skew any 66buff to any 66buff skew measurement at 1.5v ? 175 ps t ccj 66buff cycle to cycle jitter measurement at 1.5v 100 ps t pd 66in to 66buff(propagation delay) measurement at 1.5v 2.5 4.5 ns pci /pcif t dc pci /pcif duty cycle measurement at 1.5v 45 55 % t period pci /pcif period measured at crossing point v ox 30 ns t high pci and pcif high time mea surement at 2.4v 12.0 ? ns t low pci and pcif low time mea surement at 0.4v 12.0 ? ns t r / t f pci and pcif rise and fall times measured between 0.4v and 2.4v 0.5 2.0 ns t skew any pci clock to any pci clock skew measurement at 1.5v ? 500 ps t ccj pcif and pci cycle to cycle jitter measurement at 1.5v ?250ps dot_48m ac electrical specifications (continued) parameter description condition min. max. unit
cy28339 rev 1.0, november 25, 2006 page 15 of 17 test and measurement set-up for differential cpu output signals the following diagram shows lumped test load configurations for the differential host clock outputs. t dc dot_48m duty cycle measurement at 1.5v 45 55 % t period dot_48m period measurement at 1.5v 20.83 20.83 ns t r / t f dot_48m rise and fall times measured between 0.4v and 2.4v 0.5 1.0 ns t ccj dot_48m cycle to cycle jitter measurement at 1.5v ? 350 ps usb_48m t dc usb_48m duty cycle measurement at 1.5v 45 55 % t period usb_48m period measurement at 1.5v 20.82 20.83 ns t r / t f usb_48m rise and fall times measured between 0.4v and 2.4v 1.0 2.0 ns t ccj dot_48m cycle to cycle jitter measurement at 1.5v ?350ps ref t dc ref duty cycle measurement at 1.5v 45 55 % t period ref period measurement at 1.5v 69.827 69.855 ns t r / t f ref rise and fall times measured between 0.4v and 2.4v 1.0 4.0 v/ns t ccj ref cycle to cycle jitter measurement at 1.5v ? 1000 ps enable/disable and setup t pzl /t pzh output enable delay (all outputs) when xin is driven from external clock source 1.0 10.0 ns t pzl /t pzh output disable delay (all outputs) 1.0 10.0 ns t stable clock stabilization from power-up ? 3.0 ms t ss stopclock set up time cpu_stop# and pic_stop# set up time with respect to pcif clock to guarantee that the effected clock will stop or start at the next pcif clock?s rising edge. 10.0 ? ns t sh stopclock hold time 0?ns t su oscillator start-up time when crystal meets min. 40 : device series resis- tance specification ac electrical specifications (continued) parameter description condition min. max. unit measurement point 2pf cput t pcb t pcb cpuc : : : : : : measurement point 2pf figure 15. 1.0v test load termination
cy28339 rev 1.0, november 25, 2006 page 16 of 17 cput t pcb t pcb cpuc : : measurement point : : 2pf measurement point 2pf : figure 16. 0.7v test load termination 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals tdc probe out p ut under test load cap - - figure 17. for single-ended output signals
rev 1.0, november 25, 2006 page 17 of 17 cy28339 while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear inc., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions ordering information part number package type product flow cy28339zc 48-pin tssop commercial, 0 q to 70 q c cy28339zct 48-pin tssop ? tape and reel commercial, 0 q to 70 q c lead free CY28339ZXC 48-pin tssop commercial, 0 q to 70 q c cy28339zcxt 48-pin tssop ? tape and reel commercial, 0 q to 70 q c 1.100[0.043] 0.051[0.002] 0.851[0.033] seating plane 1 24 0.508[0.020] 0.500[0.019] 7.950[0.313] 0.25[0.010] 6.198[0.244] 12.395[0.488] 8.255[0.325] 5.994[0.236] 0.950[0.037] 0.500[0.020] bsc 12.598[0.496] 0.152[0.006] 0.762[0.030] 0-8 dimensions in mm[inches] min. max. max. 0.170[0.006] 0.279[0.011] gauge plane 0.20[0.008] 25 48 0.100[0.003] 0.200[0.008] reference jedec mo-153 package weight 0.33gms part # z4824 standard pkg. zz4824 lead free pkg. 48-lead (240-mil) tssop ii z4824

▲Up To Search▲

Price & Availability of CY28339ZXC

	To Download CY28339ZXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .